1. Field of Invention
The present invention relates to a forward converter with self-driven synchronous rectifiers.
2. Related Art
A forward converter can be used to convert a high DC voltage source into multiple low DC voltage sources, where the master output is regulated by a closed-loop pulse width modulation (PWM) controller and slave outputs are regulated by secondary side post regulators (SSPR).
FIG. 1 is a block diagram illustrating the master output with synchronous rectifiers. The secondary power loop comprises a secondary power winding Ts, a forward synchronous rectifier Mf, a freewheeling synchronous rectifier Mw, a power inductor L1 and a filter capacitor C1. The closed-loop PWM controller comprises three blocks: (1) an error-amplifier circuit 1 samples the output voltage V1 through a voltage divider and compares the output voltage sample with a reference voltage to generate an amplified error signal (voltage or current); (2) a control circuit 2 converts the amplified error signal into a PWM signal and (3) a drive circuit 3 converts the PWM signal into drive signals of Mf and Mw.
The block diagrams of slave outputs with diode rectifiers are shown in FIG. 2a and FIG. 2b. The secondary power loop comprises a secondary power winding Ts2, a secondary side post regulator (SSPR) S1, a forward diode rectifier Df, a freewheeling diode rectifier Dw, a power inductor L2 and a filter capacitor C2. S1 can be placed at either the high-side (FIG. 2a) or the low-side (FIG. 2b). Df can be placed at either the high-side or the low-side, depending on the materialization of S1. S1 can be implemented with either a magnetic amplifier (MA) or a controlled switch (CS). If S1 is implemented with a MA, Df must be placed at the high-side and the switch controller 4 is a reset circuit. If S1 is implemented with a CS, Df can be placed at either the high-side or the low-side and the switch controller 4 is a drive circuit. S1 blanks the leading edge of the voltage waveform across Ts2 so that the average value of the voltage waveform across Dw equals the output voltage V2. The blanking effect of S1 is illustrated with FIG. 3, where VL1 is the voltage across L1 in FIG. 1 and VL2 is the voltage across L2 in either FIG. 2a or FIG. 2b. 
During the on-interval 0≦t≦Ton, the voltage across Ts is positive with respect to its reference polarity; Mf is turned on but Mw is turned off; VL1 is positive with respect to its reference polarity; L1 stores electric energy through Ts, Mf and C1. During the blanking-interval 0≦t≦Tblank, the voltage across Ts2 is positive with respect to its reference polarity; S1 is turned off; the voltage waveform across Ts2 is blanked by S1; no current flows through Df; the continuous current of L2 forces Dw to conduct; VL2 is negative with respect to its reference polarity; L2 releases electric energy through Dw and C2. During the non-blanking interval Tblank≦t≦Ton, the voltage across Ts2 is positive with respect to its reference polarity; S1 is turned on; the voltage waveform across Ts2 is not blanked by S1; the continuous current of L2 commutates from Dw to Df; VL2 is positive with respect to its reference polarity; L2 stores electric energy through Df, Ts2, S1 and C2.
During the reset-interval Ton≦t≦Ton+Treset, the voltage across Ts is negative with respect to its reference polarity; Mf is turned off but Mw is turned on; VL1 is negative with respect to its reference polarity; L1 releases electric energy through Mw and C1; the voltage across Ts2 is negative with respect to its reference polarity; S1 is turned off; the continuous current of L2 commutates Df from to Dw; VL2 is negative with respect to its reference polarity; L2 releases electric energy through Dw and C2.
During the dead-interval Ton+Treset≦t≦Ts, the voltage across Ts is 0; Mf is turned off but Mw is still turned on; VL1 is negative with respect to its reference polarity; L1 releases electric energy through Mw and C1; the voltage across Ts2 is 0; S1 is turned off; Df is turned off but Dw is turned on; VL2 is negative with respect to its reference polarity; L2 releases electric energy through Dw and C2.
If the drive circuit 3 in FIG. 1 is based on an integrated circuit (IC), Mf and Mw are referred to as IC-driven synchronous rectifiers. If it is based on a secondary driving winding, Mf and Mw are referred to as self-driven synchronous rectifiers. In general, a drive circuit based on an IC is more complicated and expensive than a drive circuit based on a secondary driving winding. As for slave outputs, Df and Dw in either FIG. 2a or FIG. 2b suffer from higher rectifier conduction loss. Therefore, the present invention discloses a cost-effective approach to drive the self-driven synchronous rectifiers in the master output and slave outputs simultaneously.